1. Field of the Invention
The present invention relates generally to a DC-DC converter which boosts or reduces a supplied DC voltage to produce a different DC voltage. More particularly, this invention relates to improvements in reducing the power consumed in a DC-DC converter, reducing the ripple effect and shortening the rise time as characteristics of the converter's output voltage.
2. Description of the Related Art
The current popularity of portable electronic devices, like the cordless telephone, is due in part to the fact that these devices have become more compact and light. Such products commonly utilize a DC-DC converter in the power supply section of the device. From a design perspective, the output voltage from such a power supply should be stable and have as small a ripple as possible in order to improve the device's operating characteristics. It is likewise desirable that the DC-DC converter, utilized in the power supply of such devices, consume as little power as possible. Naturally, the lower the power consumption requirement of these devices, the fewer batteries are required for their operation.
FIG. 1 illustrates the electric structure of a conventional chopper type DC-DC converter. A PNP transistor 61 has an emitter connected to a power supply Vcc, and a collector connected to the cathode of a flywheel diode 62. The anode of the diode 62 is connected to an output terminal VOUT as well as to the first electrode of an output capacitor 64. An induction coil 63 is connected between the cathode of the diode 62 and the second electrode of the capacitor 64.
A regulator section includes the transistor 61, diode 62, coil 63 and capacitor 64. Normal regulator section operation results in a negative output voltage V0 appearing at the first electrode of the capacitor 64 (i.e., the output terminal VOUT). The output voltage V0 is supplied to a load resistor RL connected between the output terminal VOUT and ground.
An operational amplifier (op-amp) 65 has an inverting input terminal, a non-inverting input terminal and an output terminal. The inverting input terminal of the op-amp 65 is connected to the high potential side of a reference power supply VR4 via resistor R10, and to the output terminal VOUT via a resistor R11. The non-inverting input terminal of the op-amp 65 is grounded (i.e., V=0). The output terminal of the op-amp 65 is connected to the second electrode of the capacitor 64. As constructed, op-amp 65 therefore forms an inverting amplifier. A voltage supplied from reference power supply VR4 and the output voltage V0, divided by the resistors R10 and R11, is applied to the inverting input terminal of op-amp 65. A voltage at the output terminal of the operational amplifier 65 sets the voltage at the inverting input terminal to ground level, due to the imaginary short-circuiting of the operational amplifier 65.
A comparator 66 has an inverting input terminal connected to the output terminal of the op-amp 65, a non-inverting input terminal connected to the oscillator 67 and an output terminal connected to the base of the PNP transistor 61. The oscillator 67 supplies the non-inverting input of comparator 66 with a triangular wave signal. The comparator 66 compares the voltage at its inverting input terminal with the voltage at its non-inverting input terminal and outputs a signal that turns the transistor 61 on or off based on the results of the comparison.
When the transistor 61 is turned on, a current flows across the induction coil 63 from the power supply Vcc. This current produces a voltage across the coil 63, which is positive on the cathode side of the diode 62. Since the diode 62 initially inhibits the conduction of the capacitor 64, the voltage across the capacitor 64 will not change. A load current IR, flowing into the output terminal VOUT from the ground via the load resistor RL, allows the capacitor 64 to discharge, and thereby changes the output voltage V0. A current I1, which is the sum of the load current IR and the current flowing across the coil 63, is supplied to the output terminal of the op-amp 65.
When the transistor 61 is turned off, the current supply from the power supply Vcc to the coil 63 is blocked. As a result, a counter electromotive force, negative on the cathode side of the diode 62, is generated across the coil 63. The counter electromotive force causes a current to flow across the coil 63 via the diode 62, to charge the capacitor 64. The load current IR flows through the diode 62 and coil 63, and flows into the output terminal of the op-amp 65 as the current I1.
The voltage at the output terminal of the op-amp 65 sets the voltage at its inverting input terminal to the ground level due to the imaginary short-circuiting of the operational amplifier 65. Op-amp 65 provides a voltage relative to the output voltage V0 which varies according to the charging and discharging of the capacitor 64. In other words, the operational amplifier 65 creates a feedback of the voltage VF at the second electrode of the capacitor 64 in accordance with the output voltage V0. Consequently a ripple appears on the voltage VF at the second electrode. As a result, the output voltage V0 at the output terminal VOUT is suppressed to 1/(GA +1) where GA is the gain of the feedback system. The ripple is likewise suppressed to 1/(GA+1).
Even with a relatively small load current IR, the averaged value /VF of the voltage VF increases as shown in FIG. 2. Consequently, the power consumption of the DC-DC converter is fairly large even with a small load current IR.
With a relatively large load current IR, the ripple of the voltage VF becomes large as shown in FIG. 3. When the amplitude of the ripple increases and the voltage value temporarily falls to or below 0 volts, the output transistor (not shown) in the operational amplifier 65 becomes saturated since its operational range is only between the DC source voltage Vcc and 0 volt (ground). When saturated, however, this particular output transistor will produce an undesirable ripple on the output voltage V0 at the output terminal VOUT. To prevent this, the capacitance of output capacitor 64 is chosen to be relatively large. Using a large capacitance here results in making the rise time of the output voltage V0 undesirably long. Such a protracted rise time characteristic of output voltage V0, presents problems for using the DC-DC converter in systems requiring frequent and repeated powering on and off. In semiconductor devices, for example, the increasing trend to reduce the devices consumed power requires circuitry repeated powered on and off. The DC-DC converter as described is poorly suited for such devices.
FIG. 4 illustrates the electric structure of another typical chopper type DC-DC converter. A PNP transistor 71 has an emitter connected to a power supply Vcc, and a collector connected to the cathode of a flywheel diode 72. The anode of the diode 72 is connected to an output terminal VOUT as well as to the first electrode of an output capacitor 74. An induction coil 73 is connected between the cathode of the diode 72 and the second electrode of the capacitor 74. The second electrode of the capacitor 74 is grounded.
A regulator section includes the transistor 71, diode 72, coil 73 and capacitor 74. A negative output voltage V0 appears at the first electrode of the capacitor 74 (i.e., the output terminal VOUT). The output voltage V0 is supplied to a load resistor RL connected between the output terminal VOUT and ground.
A first comparator 75 has a non-inverting input terminal connected to an oscillator 77, and an inverting input terminal connected to the high potential side of a reference power supply VR5. The oscillator 77 produces a square-wave or rectangular wave signal and sends it to the non-inverting input terminal of the comparator 75.
A second comparator 76 has a non-inverting input terminal connected to a triangular wave generator 78, and an inverting input terminal connected to the output terminal VOUT. The triangular wave generator 78 converts the rectangular wave signal from the oscillator 77 into a triangular wave, which is in turn output to the non-inverting input terminal of the second comparator 76. The output terminals of the comparators 75 and 76 are connected to a NAND gate 81 via inverters 79 and 80, respectively. The output terminal of the NAND gate 81 is connected to the base of the PNP transistor 71.
FIG. 5 is a detailed electric circuit diagram showing the inverters 79 and 80 and the NAND gate 81. A first NPN transistor 83 has a base connected to the first comparator 75, a collector connected via a constant current source 82 to the power supply Vcc, and an emitter connected to the ground. A second NPN transistor 84 has a base connected to the second comparator 76, a collector connected via the constant current source 82 to the power supply Vcc, and an emitter connected to the ground. A third NPN transistor 85 has a base connected to the collectors of both NPN transistors 83 and 84, a collector connected to the base of the PNP transistor 71, and an emitter connected to the ground.
The third NPN transistor 85 is turned on by a constant current I0 from the constant current source 82 only when the outputs of the comparators 75 and 76 are both low. When the NPN transistor 85 is turned on, the collector current of this transistor 85 or a base current IB of the transistor 71 is produced, and turns on the transistor 71 on.
With the transistor 71 turned on, a current IC flows across the induction coil 73 from the power supply Vcc. This current IC produces a voltage across the coil 73, positive on the cathode side of the diode 72. Since the diode 72 at this time hinders the current flowing through the capacitor 74, the charge on the capacitor 74 will not change. A load current IR is supplied to the capacitor 74 via the output terminal VOUT from the load resistor RL. This allows the capacitor 74 to be charged, which changes the output voltage V0.
When the output of one of the comparators 75 and 76 is high, the associated NPN transistor 83 or 84 receiving the high-level output is turned on. The constant current I0 of the constant current source 82 flows through the conducting NPN transistor 83 or 84. As a result, the third NPN transistor 85 is turned off. This prevents the base current IB of the transistor 71 from flowing, thus turning off the transistor 71.
When the transistor 71 is turned off, the current supply to the coil 73 from the power supply Vcc is blocked. As a result, a counter electromotive force, negative on the cathode side of the diode 72, is generated across the coil 73. This counter electromotive force causes a current to flow across the coil 73 via the diode 72, thus charging the capacitor 74. The load current IR escapes to the ground through the diode 72 and coil 73.
The PNP transistor 71 is turned on or off by a constant base current IB proportional to the constant current I0. The duration that the transistor 71 is on is controlled in accordance with the output voltage V0 that varies with changes in load current IR. The duty ratio of the output signal of the second comparator 76 changes based on the variable output voltage V0. This change in the duty cycle changes the harmonic component of the current IC flowing through the transistor 71. Unfortunately, this variation in harmonic component would in turn produce an effect in any circuit coupled to the DC-DC converter, as for example, a radio frequency circuit.
When the load current IR is small, the current IC flowing across the coil 73 decreases to a relatively small value when the transistor 71 switches on. As the base current IB is constant, however, IB becomes larger than IC, rendering the transistor 71 in an oversaturated state. This consequently delays the switching action of the transistor 71 in the DC-DC converter. Also because the base current IB is larger than needed to permit the flow of the current IC power is wasted due to the surplus current. Additionally, with a decreasing switching speed, the DC-DC converter can not be used for high frequency switching. To permit high frequency switching, the inductance across coil 73 should be relatively large. This would however prevent a reduction to be made in the size of the electronic device incorporating such a DC-DC converter.
If the transistor 71 is integrated together with other devices on a P type substrate, the transistor 71 has a PNP structure in which P type regions, used for the emitter and collector, are formed in an N type well that forms the base. With this PNP structure, when the base current IB becomes larger than the current IC, the emitter and collector have nearly the same potentials. The potentials of both are higher than the potential of the P type substrate. This in effect creates a parasitic PNP transistor. As a result, a large current is likely to flow through the P type substrate, further increasing a waste in the power consumed by the DC-DC converter.